(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to decrease the capacitance between a bit line structure and a capacitor structure, used as elements in a dynamic random access memory (DRAM), cell.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed the semiconductor industry to increase device performance while still reducing processing costs. The use of smaller device features allow reductions in performance degrading parasitic junction capacitances to be realized, resulting in the desired, improved performance objective to be realized. In addition the use of sub-micron features allow an increased number of smaller semiconductor chips to be obtained from a specific size starting substrate, thus reducing the processing cost of a specific semiconductor chip. However in contrast to the reduction in parasitic junction capacitance for a device formed with sub-micron features, a reduction in the space between a bit line structure and a capacitor structure, for a capacitor under bit line (CUB), DRAM device, is also encountered, thus resulting in unwanted capacitance increases, and in turn deleteriously influencing device performance.
This invention will describe a novel process sequence used to reduce the capacitance between the bit line and capacitor structures of CUB DRAM devices, via use of air gaps created in portions of the spaces between these DRAM elements. The air gaps are created as pseudo spacers, formed on the sides of the openings used to accommodate subsequent capacitor structures. The use of air gap isolation between the bit line and capacitor structures allows the capacitance of these closely placed elements, introduced via the use of sub-micron features, to be minimized. Prior art, such as Lee, in U.S. Pat. No. 6,090,698, describes the use of horizonal air gaps located between dielectric layers, to reduce the capacitance of a composite dielectric layer, however that prior art does not offer the novel process sequence described in the present invention in which air gap regions are formed along the vertical sides of a DRAM a capacitor opening, via formation of, and removal of, sidewall spacers.
It is an object of this invention to fabricate a capacitor under bit line (CUB), DRAM device, using sub- micron features.
It is another object of this invention to reduce the capacitance between a bit line contact structure and capacitor structures via formation of air gap isolation regions in portions of the space located between these structures.
It is still another object of this invention to form the air gap isolation regions via formation of a spacer shape on the sides of a capacitor opening, followed by selective removal of the spacer shape, performed after formation of the capacitor structure, creating the desired air gap regions.
In accordance with the present invention a method of forming air gap isolation regions in portions of the spaces located between a bit line contact structure and DRAM capacitor structures, is described. After formation of transfer gate transistor structures, on a semiconductor substrate, conductive plug structures are formed overlying source/drain regions located in portions of the semiconductor substrate not covered by the transfer gate transistors. After deposition of a first insulator, capacitor openings are formed in the first insulator layer, exposing portions of the top surface of a group of conductive plug structures, which will subsequently be used to underlay capacitor structures. Insulator spacers are next formed on the vertical sides of the capacitor openings, followed by the formation of capacitor structures located in the capacitor openings, with a top portion of the capacitor structure partially overlying the top surface of the first insulator layer. The first insulator layer is next selectively etched backed, exposing a top portion of the insulator spacers, followed by selective removal of the entire insulator spacers, resulting in air gaps located between the capacitor structures, in the capacitor openings, and the thinned first insulator layer. A second insulator layer, exhibiting poor coverage characteristics, is then deposited on the thinned first insulator layer and on the capacitor structures, however not filling the air gaps, thus providing a seal for air gap regions. A bit line contact opening is then formed in the second insulator layer, and in the thinned first insulator layer, between the capacitor structures, exposing the top surface of a bit line conductive plug structure. Formation of a bit line contact structure is then accomplished in the bit line contact hole opening, with the capacitance between the bit line contact structure and the capacitor structures reduced via use of the air gap isolation regions.